1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, in particular, to a method of manufacturing a semiconductor device in which a region having a capacitor such as a memory cell part and a region having no capacitor such as a logic circuit are disposed on the same semiconductor substrate.
2. Description of the Background Art
In semiconductor devices, specifically dynamic RAMs (DRAMs), the number of manufacturing steps and manufacturing time are increasing with increasing the tendency of high integration and large capacity. As a solution, it is the most important to simplify the manufacturing steps.
A conventional method of manufacturing a DRAM having a cylindrical capacitor will be described by using FIGS. 16 to 24, which are sectional views showing a sequence of manufacturing steps. FIGS. 16 to 24 only partially show the configuration of the DRAM, and the number of the individual elements etc. are not to be construed as a limiting value.
FIG. 16 is a partial sectional view showing a DRAM 90 having a memory cell region MR and a peripheral circuit region LR that is formed in the periphery of the memory cell region MR and does not have any capacitor such as a logic circuit, sense amplifier, and decoder. The final configuration of the DRAM 90 is given in FIG. 24 showing the final step.
In the step of FIG. 16, a silicon substrate 1 is prepared. In a main surface of the silicon substrate, an element isolation insulating film 2 is selectively formed to define the memory cell region MR and peripheral circuit region LR, and also define an active region AR in the memory cell region MR and peripheral circuit region LR, respectively.
Subsequently, by a conventional technique, the following components are formed to obtain an MOS transistor in the active region AR of the memory cell region MR. That is, source/drain regions 11, 12, and 13 are selectively formed in the substrate surface. A gate insulating film 21 is formed so as to extend above between the ends of the source/drain regions 11 and 12, and between the ends of the source/drain regions 12 and 13. A gate electrode 22 is disposed on the gate insulating film 21. Further, a sidewall insulating film 23 is formed so as to cover the side surface of the game electrode 22.
On the other hand, the following components are formed to obtain an MOS transistor in the active region AR of the peripheral circuit region LR. That is, source/drain regions 14 and 15 are selectively formed in the substrate surface. A gate insulating film 31 is formed so as to extend above between the ends of the source/drain regions 14 and 15. A gate electrode 32 is disposed on the gate insulating film 31. Further, a sidewall insulating film 33 is formed so as to cover the side surface of the game electrode 32.
Then, an interlayer insulting film 3 is formed, such as by the use of a silicon oxide film, so as to cover the memory cell region MR and peripheral circuit region LR by CVD (chemical vapor deposition) method, for example.
In the memory cell region MR, a bit line 42 is selectively formed in the interlayer insulating film 3 overlying the source/drain region 12. The bit line 42 is electrically connected via a contact plug 41 to the source/drain region 12.
In the step of FIG. 17, a resist is applied to the entire surface of the interlayer insulating film 3, and a resist pattern for forming a contact plug is transferred to form a resist mask RM11 by photolithography technique. In FIG. 17, the resist mask RM11 has a resist pattern for disposing a contact hole CH11 only in the interlayer insulating film 3 of the memory cell region MR.
Thereafter, an anisotropic dry etching using the resist mask RM11 is performed to form the contact hole CH11 extending through the interlayer insulating film 3 to the source/drain regions 11 and 13.
The resist mask RM11 is then removed. In the step of FIG. 18, for example by CVD method, a polysilicon film is formed over the entire surface of the interlayer insulating film 3 in order to fill in the contact hole CH11. The polysilicon film on the interlayer insulating film 3 is then removed by CMP (chemical mechanical polishing), for example, and a contact plug 51 serving as an electrode plug is formed in the contact hole CH11.
Thereafter, an etching stopper film 4 is formed, such as by the use of a silicon nitride film, over the entire surface of the interlayer insulating film 3.
In the step of FIG. 19, an interlayer insulating film 5 is formed, such as by the use of a silicon oxide film, over the entire surface of the etching stopper film 4. A resist is applied over the entire surface of the interlayer insulating film 5. A resist pattern for forming a capacitor is transferred to form a resist mask RM12 by photolithography technique. This resist pattern has such a pattern that is opened at a portion corresponding to above of the contact plug 51.
In the step of FIG. 20, an anisotropic dry etching using the resist mask RM12 is performed to form a cylindrical opening OP11 extending through the interlayer insulating film 5 and etching stopper film 4 to the interlayer insulating film 3. The opening OP11 is disposed so as to correspond to a region for forming the contact plug 51, and the top surface of the contact plug 51 is exposed to the bottom part of the opening OP11.
When performing etching to the interlayer insulating film 5, the etching condition is selected such that the etching is stopped at the etching stopper film 4.
The opening OP11 is formed so as to match the contour of a cylindrical capacitor to be formed later, in order that the cylindrical capacitor is formed within the opening OP11.
The resist mask RM12 is then removed. In the step of FIG. 21, a capacitor lower electrode 52 is obtained by forming a polysilicon film along the inner wall of the opening OP11 by CVD method, for example.
Thereafter, a capacitor dielectric film 53 is formed along the surface of the capacitor lower electrode 52. Further, a capacitor upper electrode 54 is obtained by forming for example a polysilicon film extending from the upper surface of the capacitor dielectric film 53 to above the interlayer insulating film 5 around the opening OP11. This results in the cylindrical capacitor CP, which is also called xe2x80x9cinterior type.xe2x80x9d
In the step of FIG. 22, an interlayer insulating film 6 is formed, such as by the use of a silicon oxide film, over the entire surface of the memory cell region MR and peripheral circuit region LR.
In the step of FIG. 23, in the memory cell region MR, an anisotropic dry etching is performed to form a contact hole CH12 extending through the interlayer insulating film 6 to the capacitor upper electrode 54 overlying the interlayer insulating film 5. In the peripheral circuit region LR, an anisotropic dry etching is performed to form a contact hole CH13 extending through the interlayer insulating films 6 and 5, etching stopper film 4, and interlayer insulating film 3 to the source/drain regions 14 and 15.
In the step of FIG. 24, for example by sputtering method, the contact holes CH12 and CH13 are filled with a metal film (e.g., tungsten film), thereby to form contact plugs 61 and 71, respectively. The DRAM 90 is obtained by patterning metal wiring layers 62 and 72 such that they are connected to the contact plugs 61 and 71, respectively. Although an interlayer insulating film and wiring layer may be further disposed on the interlayer insulating film 6 in some cases, their depict and description are omitted here.
As described above, the conventional manufacturing method of the semiconductor device having the stacked capacitor requires at least two photolithography processes and a plurality of anisotropic dry etching processes in order to form the contact plug 51 as electrode plug and the cylindrical capacitor CP. Therefore, this method has the disadvantage that the manufacturing steps are complicated and the manufacturing cost is increased.
Further, as described in connection with FIG. 23, when forming the contact hole CH13 so as to reach the source/drain regions 14 and 15 in the peripheral circuit region LR, namely the region where no capacitor is formed, not only the interlayer insulating films 3, 5, and 6, but also the etching stopper film 4 is removed. At this time, since the silicon oxide film and silicon nitride film have different anisotropic dry etching conditions, it is necessary to change the etching conditions depending on the etching object. This contributes to the complicated manufacturing steps.
Furthermore, after forming the contact hole CH13, wet etching using chemicals such as hydrofluoric acid (HF) is performed to remove native oxide to be formed on the surface of the silicon substrate 1 that corresponds to the bottom surface of the contact hole CH13. At this time, the interlayer insulating films 3, 5, and 6, being silicon oxide film, are also slightly etched. On the other hand, the etching stopper film 4, being silicon nitride film, is hardly removed. As the result, the etching stopper film 4 projects like a visor in the contact hole CH13, as shown in FIG. 25.
In this state, as described in connection with FIG. 24, even if the contact hole CH13 is filled with the metal material, no metal film is formed at least immediately under the visor of the etching stopper film 4 (see FIG. 26), thus lowering the coverage. In some cases, no metal film might be formed in the lower layer than the visor of the etching stopper film 4.
It is an object of the present invention to provide a semiconductor device manufacturing method with which the numbers of photolithography and anisotropic dry etching processes are reduced to simplify the manufacturing steps, and it is avoided that the presence of an etching stopper film complicates manufacturing steps in a region where no capacitor is formed, and that the presence of the etching stopper film also causes malfunction in a contact plug.
An aspect of the semiconductor device manufacturing method of the present invention is intended for a method of manufacturing a semiconductor device of a multilayer structure including a circuit region having a capacitor. This method has the following steps (a) to (f). The step (a) is to form a first interlayer insulting film on a semiconductor substrate. The step (b) is to form an etching stopper film on the entire surface of the first interlayer insulating film. The step (c) is to pattern, in the circuit region having the capacitor, the etching stopper film so as to have a first opening of which opening area is approximately the same as the sectional area of a first contact plug electrically connecting a lower electrode of the capacitor and the configuration of a lower layer than the etching stopper film. The step (d) is to form a second interlayer insulating film on the etching stopper film. The step (e) is to form at a time, in the circuit region having the capacitor, a capacitor opening for defining the contour of the capacitor and a first contact hole for forming the first contact plug by removing, by an anisotropic dry etching, a predetermined region of the second interlayer insulating film including above the first opening until the etching stopper film is exposed, and continuing the etching to remove the first interlayer insulating film below the first opening. The step (f) is to form the capacitor in the capacitor opening.
The first contact hole for forming the first contact plug in the circuit region having the capacitor and the capacitor opening for forming the capacitor can be formed by performing photolithography two times and anisotropic etching two times. Therefore, the manufacturing steps can considerably be simplified to reduce the manufacturing cost.